Implementation and Utilization of Hardware Parallelism in Modern CPU Architectures
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2024
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Haverford College. Department of Computer Science
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Thesis
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Award
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eng
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Open access
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Abstract
For at least the past three decades, nearly all computer architectures have made use of pipelining, a concept that has proven indispensable in improving the efficiency of computer processors, regardless of the application. Pipelining improves the throughput of an instruction sequence by running instructions in mutually independent stages, thus achieving what is called instruction level parallelism (ILP). This paper provides an overview of how ILP has been utilized to develop more efficient processors, reviewing a selection of papers influential to its use. To this end, the tradeoffs between out-of-order and in-order execution are considered. Finally, the most recent work being done to improve instruction level parallelism is discussed.