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Pipelining: Hazards, Methods of Optimization, and a Potential Low-Power Alternative

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dc.contributor.advisor Wonnacott, David G. Lutze, Solomon 2011-10-18T20:04:45Z 2011-10-18T20:04:45Z 2011
dc.description.abstract This paper surveys methods of microprocessor optimization, particularly pipelining, which is ubiquitous in modern chips. Pipelining is a method of executing instructions in stages, so multiple instructions can be operating in the pipeline simultaneously and allow the chip to use its resources more efficiently. This system creates hazards, which are potential incorrect answers: these can be structural hazards (insufficient logical hardware to process all queued instructions), data hazards (data is read, written, and overwritten incorrectly), or branch hazards (the pipeline does not know whether to load target or fall-through instructions). These complexities slow down the pipeline, so in order to improve speed against all constraints, additional hardware (and therefore extra energy and heat) are required to detect potential hazards and resolve them. This work informs our study of an architecture, conceived of by Dave Wonnacott, that has a more complex and subdivided instruction set. This shifts much of the complexity from hardware to compiler design, which allows for smaller chips. Smaller chips have lower heat and energy costs, which is itself valuable but also creates the potential for running multiple chips at the same cost as one larger (pipelined) chip. en
dc.description.sponsorship Haverford College. Dept. of Computer Science en
dc.language.iso en_US en
dc.subject.lcsh Pipelining (Electronics)
dc.subject.lcsh Microprocessors -- Design
dc.title Pipelining: Hazards, Methods of Optimization, and a Potential Low-Power Alternative en
dc.type Thesis (B.S.) en
dc.rights.access Open Access

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